[quote:a0a527a960="i.dobson"]It could be a timing problem. You might be just inside the limit with your ISP.[/quote:a0a527a960] And care has to be taken that soft-serial handling completely within ISR may keep INTF0 set.
INTF0 is initially cleared by execution of the INT0-vector, but set again by pin-toggling of incoming serial data. This leads to another execution of named ISR immediately after leaving it, while then no data is available and it gets stuck. Solution is to clear INTF0 just before leaving the ISR by writing an 1 to it.
Software serial port is just that. Serial communication needs fairly accurate timing to work and if your ISR (interupt handling code) takes too long it could delay the Serial code enough to corrupt communications.
How long does you ISR run (Show us some code, hint, hint).
I once wrote a software/interrupt driven serial input (Using a Timer and a Pin Change interrupt). I see if I can find the code when I get home this evening.
I'm attempting to use software serial ports and Timer0 in 1 second interrupt mode together in an ATtiny45, but it does not work. They both work separately, but not when combined in the same firmware. I vaguely recall seeing somewhere that the two cannot be used at the same time, but I cannot find that article/post anywhere. Can someone please advise whether this is correct?
[b:cf038c20b5][color=red:cf038c20b5](BASCOM-AVR version : 126.96.36.199 , Latest : 188.8.131.52 )[/b:cf038c20b5][/color:cf038c20b5]
I'm reasonably certain that all Series A (1 or 3) XMega have the same registers for the USART as Master SPI. The excerpt from the data sheet shows only UDORD as the Reg.Bit that allows for LSB or MSB shifting. I have confirmed that it works.
I think the problem I'm having is related to matching the Config Baud Rate with Register Values. When a Byte transmitted out, there is some type of problem that I need to understand. Don't know if I'm creating the problem, or if it is Bascom.
One more note: Bascom allows (without throwing an error): [code:1:d5ef001d1d] Config [x]1, 3, 5, 7 = 115200 , Mode = SPI , Parity = None , Stopbits = 1 , Databits = 8[/code:1:d5ef001d1d] ... but these do not have underlying SPI capability and will not work.
[quote:7f8a55827f="enniom"]I'm not able to find where this is set.[/quote:7f8a55827f] In my code - however for a different processor - I've defined the bit-names myself, if you resolve my constant definitions you get: USARTD0_CTRLC.7 and 6. I did not check whether bit-names are equal for xm192a3u, but thought you will look up my used xm128a1d and draw the comparison.